EtherCAT Master IP for FPGA

EtherCAT Master IP compatible with Intel FPGA and Xilinx FPGA. It includes API to use EtherCAT Master IP and sample software, hence can be used immediately after purchase.

Features of Hardware Master

• Jitter do not occur even in μs order cyclic cycles due to hardware IP
• Design of slave processing time is easier, because the communication cycle is fixed
• No necessity to consider the system’s control application load for EtherCAT communication
• Do not require CPU resources to create and analyze packets
• EtherCAT implemention is possible with same design policy as systems, that used conventional communication ICs