We offer EtherCAT master solutions tailored to your needs, from high-performance FPGA IP to flexible open-source soft masters.
EtherCAT Master IP compatible with Intel FPGA and Xilinx FPGA. It includes API to use EtherCAT Master IP and sample software, hence can be used immediately after purchase.
Features of Hardware Master
Jitter do not occur even in μs order cyclic cycles due to hardware IP
Design of slave processing time is easier, because the communication cycle is fixed
No necessity to consider the system’s control application load for EtherCAT communication
Do not require CPU resources to create and analyze packets
EtherCAT implemention is possible with same design policy as systems, that used conventional communication ICs
For customers who want to achieve ultra-high-speed control on the order of
microseconds.
Our FPGA EtherCAT Master IP solves your challenges with
deterministic real-time performance and reduced CPU load.
This is a hardware IP compatible with Altera/AMD FPGAs. By processing the EtherCAT master protocol
on the FPGA, it significantly reduces CPU load and achieves high-speed, high-precision communication
on the order of microseconds.
Key Features
Improved main application performance by reducing CPU load
Stable communication cycle with low jitter
High-precision time synchronization (Distributed Clock) support (Pro version)
For customers who want a flexible EtherCAT master with low cost.
Achieve
rapid implementation and custom development by leveraging open source.
We build an EtherCAT master in a Linux environment using open-source software. This is a low-cost
solution ideal for evaluation, implementation consideration, and technology acquisition. We will
port it to your board as a custom development.
Key Features
Open-source environment with Linux and SOEM
Hardware support through our BSP development service
Low-cost EtherCAT master environment construction
FPGA IP vs. Open-Source Soft Master
Item
FPGA EtherCAT Master IP
Open-Source EtherCAT Soft Master
Performance (Real-time)
◎ Excellent (microsecond-order jitter)
〇 Good (millisecond-order, improvable with
kernel patch)
CPU Load
◎ Very Low (hardware processing)
△ High (software processing)
Implementation Cost
△ High (IP license fee)
◎ Very Low (open source)
Development Flexibility
〇 High (customizable with API)
◎ Very High (source code can be modified)
Development Difficulty
△ High (requires FPGA knowledge) *1
〇 Relatively Low (requires Linux knowledge)
Optimal Use Case
High-precision synchronous control, systems where CPU load must be avoided
Cost-sensitive systems, systems requiring flexible development, evaluation/learning
*1: We also offer porting services.
EtherCAT Master IP Specifications
Item
Content
Communication Protocol
EtherCAT (IEC 61158-3/4/5/6-12) CoE support
Transmission Speed
100Mbps (100BASE-TX) support
Number of Communication Ports
2 ports (Pro version only)
Process Communication Cycle
62.5 μs to 65,535 μs Depends on data size and number of slaves
Functions
High-precision time synchronization (DC) function (Pro version only)
Redundancy function (Pro version only)
Retransmission function (Pro version only)
Packet generation/analysis function
Process communication (periodic communication) function
Mailbox communication function
FoE function
EtherCAT Master IP Introduction
This is a product introduction for our EtherCAT Master IP.
EtherCAT Multi-Master
This is a control demo video using a multi-master setup.
Master IP Application Example: Solving Challenges with a Multi-Master Architecture
For customers facing complex challenges such as system simplification, fault tolerance, and
network synchronization. A multi-solution that controls multiple networks with a
single IC provides the optimal solution. System design simplification, fault tolerance,
inter-network synchronization, traffic distribution, etc. – our FPGA IP allows for multiple
networks. We propose the optimal EtherCAT master solution according to your system requirements,
performance, cost, and development schedule. We also offer flexible licensing models for our FPGA
IP, from single products to series products.
Case Studies
Master IP Implementation Experience
Manufacturer
Device
Experience
Altera
Cyclone5, MAX10, Agilex5
Experience
AMD
Zynq-7000, UltraScale+ MPSoC
Experience
EFNIX
Titanium
Planned
Supported OS
OS
Notes
Linux + Xenomai
Standard
uITRON
Standard
FreeRTOS
Custom experience
Toppes
Custom experience
*: Please contact us for details on FPGA and OS combinations.
OpenAMP Integration
We implemented an EtherCAT network on an AMD Zynq using OpenAMP with Linux and uITRON, operated via a
web UI and Ethernet communication from a host device.
EtherCAT Slave Board Inspection Jig
We developed an inspection jig for EtherCAT slave boards using a soft master. By leveraging the
features of EtherCAT and FPGA-based I/O testing, we increased productivity by inspecting many slave
boards at once.
FAQ
Should I choose the FPGA hard master or the open-source master?
The choice depends on your requirements. If you need periodic communication on the order of
microseconds, the FPGA hard master is optimal. On the other hand, if you want to keep
running costs down, want to customize flexibly, or for evaluation/learning purposes, the
open-source master is suitable. Please also refer to the comparison table above.
Can I get an evaluation environment with a soft master right away?
We are currently preparing it. Please wait a little longer for it to become available.
Which FPGA devices does the hard master support?
We have experience with Altera’s Cyclone series, MAX10, Agilex5, and AMD’s Zynq-7000,
UltraScale+ MPSoC. For other devices, please feel free to contact us.
Can the hard master be used with OSes other than Linux?
Yes, it is possible. We support Linux and μITRON as standard, but we also offer porting to
other RTOSs such as FreeRTOS and TOPPERS as a custom service. Please feel free to consult
with us. Note that bare metal is not supported.
What is the licensing for the hard master?
Please contact us with your intended use. We will propose a license that suits your purpose,
such as a free evaluation license or a research license.
